Silicon Frontline Technology’s first tools verify IC post layout
Startup Silicon Frontline Technology, Inc. has announced its first products for post-layout verification: F3D (Fast 3D) for fast 3D extraction and R3D (Resistive 3D) for 3D extraction and analysis of large resistive structures like power devices.
The products incorporate patent-pending 3D technology to deliver a “Guaranteed Accurate” solution for full-chip, post-layout verification. The tools work in industry standard flows which allows for simpler adoption and quicker closure, with guaranteed accuracy, of the post-layout verification loop, according to the company.
Silicon Frontline was founded in 2007 by former EDA software and post-layout verification experts CEO Yuri Feinberg and vice president of Engineering Andrei Tcherniaev, with first round funding led by ID Ventures America.
Feinberg and Tcherniaev co-founded Nassda, which was acquired by Synopsys, and also were the original developers of HSIM, the EDA industry’s first hierarchical circuit simulator. At Frontline, they are joined by Chief Scientist Maxim Ershov, former professor at Univ. of Aizu, Japan and Georgia State University.
“We founded Silicon Frontline with the goal of moving post-layout verification technology to the next level,” said Feinberg. “We want EDA users to experience what hasn’t been possible until now—Guaranteed Accuracy.”
Patrick O’Connor, VP Engineering at Canesta, a developer of 3D image sensors, endorsed the results of using Frontline’s tools: “Traditional extraction technology could not model our design with sufficient confidence. With Silicon Frontline’s 3D software, we match simulations to silicon, providing us the shortest and highest confidence path to quality and reliability.”‘
The post-layout verification software uses Monte Carlo technology to extract parasitics. Users specify the level of accuracy desired and then run the software until the desired accuracy is achieved.
Guaranteed accuracy is demonstrable using a Field Solver run repetitively with denser grids. As the density increases the result converges to the F3D answer.
Feinberg said that the software has been qualified by major foundries for accuracy, performance, and capacity as well as integration with major physical verification systems for both mature process technology or advanced process technologies such as 40nm or below.
Silicon Frontline’s 3D technology eliminates the performance and capacity issues inherent in older Field-Solver technology and accomplishes full-chip extraction with Field-Solver accuracy.
Typical examples of F3D running with “guaranteed accuracy” are a 65nm SOC run in under 10 hours, MOM Caps run in under 3 minutes which take over 7 hours with standard field solvers and a 40nm design, where F3D delivered results within 2 percent of silicon, competing tools were up to 30 percent off.
Feinberg claims these results are not possible with other commercial tools available today that promote speed and accuracy.
The tools technology is a combination of the Monte Carlo method with a 3D geometric engine. This combo yields significant performance improvement and handles additional issues such as thickness variation due to Chemical Mechanical Polishing (CMP), width variation due to optical and other manufacturing effects.
The software generates a fully annotated Spice netlist with parasitics for use by downstream tools used by post-layout verification engineers.
F3D is ideally suited for sensitive analog circuits where coupling is a challenge — ADCs, DACs, differential signals, image sensors, RF and high speed designs using MIM/MOM Caps (Metal-Oxide-Metal/Metal-Insulator-Metal capacitors) and 3D devices.
Meanwhile, R3D’s target applications include discrete or embedded power devices, where efficiency and reliability are important, as well as designs requiring analysis of large metal interconnects.
This article originally ran on EE Times.