Silicon Frontline Technology, Inc. (SFT), an Electronic Design Automation (EDA) company in the post-layout verification market focused on solutions for nanometer design applications, is attending the 48th Design Automation Conference (DAC) in San Diego and will show its newest product H3D, the industry’s first commercial 3D hierarchical extractor for post-layout verification. H3D offers hierarchical parasitic extraction, hierarchical netlisting, unlimited capacity and field-solver accuracy. H3D works with design flows from the industry’s leading suppliers.
About Silicon Frontline’s Products and Guaranteed Accuracy
Silicon Frontline’s post-layout verification software delivers Guaranteed Accuracy, full-chip capacity and performance at least 20 times faster than other commercial field solvers. Users specify the level of accuracy desired, net by net, at the block level or with regular expressions. In this way, the resulting parasitics are guaranteed correct within the specified accuracy range for better design quality.
Silicon Frontline’s software has been used to accurately verify over 300 electronic designs to date. The company’s customers use its software to analyze power devices, improve image sensors, ADCs, flash memories, differential signals and nanometer and Analog Mixed Signal (A/MS) designs. The customer list includes 10 of the world’s top 30 semiconductor companies. In addition, leading foundries have validated Silicon Frontline’s products for use with their nanometer design technologies and reference flows.
F3D (Fast 3D) is used for fast 3D extraction and R3D (Resistive 3D) is used for 3D extraction and analysis of large resistive structures. F3D is chosen for its nanometer and Analog Mixed Signal (A/MS) design verification accuracy, and R3D for analysis that leads to improvements in the reliability and efficiency of semiconductor power devices.
