- Performs full-chip ESD simulation for HBM and CDM events.
- Simulates all pad-to-pad combinations.
- Provides stress check for all non-ESD devices.
- Supports multiple model formats including TLP measurements.
- Reports all interconnect and device issues.
- Automated support for new technologies, proven on the latest nodes.
- Includes inductance, inductors and capacitance in analysis.
- Supports IP validation prior to full chip integration.
Resources
- A New Full-Chip Verification Methodology to Prevent CDM Oxide Failures
- Enablement, Evaluation and Extension of a CDM ESD Verification Tool for IC Level
- Full-Chip CDM Analysis: Is Static Simulation Enough?
- Full Chip CDM Simulation With Package Layout Included for Connectivity and Charge Distribution
- Novel Full-chip Verification Methodologies for Domain-crossing and Transient Latch-up Damage Prevention
- System Aware ESD Design
