SoC Power Network Analysis
Full-Chip ESD Solution
- EDA Software for Verification of Metal Interconnects in ESD Protection Networks at Chip, Block, and Cell Level
- Enablement, Evaluation and Extension of CDM ESD Verification Tool for IC Level
- Full-chip CDM Analysis: Is Static Simulation Enough?
- Comprehensive ESD/Latch-up Reliability Verification for IP and SoC Designs
- Full-chip CDM Simulation with Package Layout Included for Connectivity and Charge Distribution
- Novel Full-chip Verification Methodologies for Domain-crossing and Transient Latch-up Damage Prevention
- System Aware ESD Design
- A New Full-Chip Verification Methodology to Prevent CDM Oxide Failures
