Silicon Frontline Technology is proud to announce that they are a recipient of 43rd Annual EOS/ESD Symposium Outstanding Paper Award for a paper titled “Enablement, Evaluation and Extension of a CDM ESD Verification Tool for IC Level.” The paper was co-authored with Infineon Technologies and Technical University of Munich.
“It is a great honor to be awarded this recognition for our collaborated work with Infineon and Technical University of Munich and highlighting the capabilities and results of our CDM ESD solution,” said Dermott Lynch, COO of Silicon Frontline Technology.
Silicon Frontline’s ESRA (Electrostatic Reliability Analysis) is a full-chip ESD analysis solution. It identifies weak points in ESD protection circuit and supports ESD sign-off for both HBM and CDM standards. ESRA delivers extraction, analysis, and debugging capabilities in one integrated environment with the capacity to analyze the full-chip, validated to 15B transistors. Highlighted violations permit engineers to perform corrections at any time in the design process.
