Silicon Frontline delivers the only full-chip ESD solution available for the verification of interconnects, ESD devices and core devices for HBM (Human Body Model) and CDM (Charged Device Model) events. Silicon Frontline ESD solution ensures that ESD design guidelines are met by highlighting weak areas of the design, pinpointing susceptible devices and providing reports of current density violations and high resistance paths.

ESD failures account for over 25% of semiconductor failures, especially for newer technologies and larger dies. ESD failures can occur in metal interconnects, ESD devices, and core devices. Packaging choices can also impact the effect of ESD. Metal interconnect is a critical part of the ESD discharge path, yet it is often evaluated manually or with tools that are inadequate to handle large complex chips. ESD protection devices are large and thus requires optimal placements for managing die size and in turn product cost.

ESD solutions from Silicon Frontline performs transient simulation of the full-chip and the package, analyzing all the interconnects and devices including inductors, inductance and capacitors. It performs analysis on both pre- and post-LVS clean layouts, allowing quick identification and correction of problems. A hierarchical debugging methodology provides both telescopic and microscopic views of the design, giving the engineers easy access to the level of details required to effectively fix issues. Silicon Frontline ESD product is easy to setup and delivers the best performance and the highest capacity to help ensure design reliability against ESD events.