Fast and Reliable Full-Chip Analysis from Planning to Tape-out
Silicon Frontline delivers fast, reliable, and easy-to-use full-chip IR drop, EM, and point-to-point resistance analyses solutions. Its’ multiple modes of operation provide the necessary data to understand and correct power network issues. Usable throughout the entire physical design process, Silicon Frontline SoC solution quickly highlights problematic networks in a graphical viewer, allowing engineers to easily identify fixes.
Designing robust power nets capable of delivering the necessary levels of current to all areas of the die is essential for the reliability of SoC. Inadequate power network can result in IR drop that impacts chips’ functionality and/or timing as well as EM-driven failures. Yet it is difficult for engineers to determine which parasitics are critical for reducing IR-drop or EM violations. Analog/mixed-signal ICs, memories and image sensors with complex non-orthogonal routing can further complicate extraction and analysis. In addition, meeting on-time silicon delivery schedule requires layout issues to be addressed early in the design process.
SoC solutions from Silicon Frontline delivers a comprehensive and flexible full-chip power network analysis. Its’ resistance mapping is the only tool available to show distributed resistance across the entire network, highlighting the origin of the problem and allowing the engineers to quickly identify and fix main contributors in point-to-point resistance problems. Interconnect extraction and exhaustive analysis help ensure robust and reliable power delivery network as well as verify completeness of ESD protection network. From early physical design to post-layout verification, Silicon Frontline solutions provide unlimited capacity, fast turnaround time, and ease-of-use for the delivery of reliable SoC designs.
- Quickly identify main contributors of power net failures with full-chip point-to-point resistance analysis.
- Early and fast analysis allows for “What-if” testing throughout the design flow.
- Straightforward verification of complex operating modes enable robust power network design.
- Mapping results highlight problems caused by dog-boning, lack of vias and long narrow tracks.
- Early analysis is enhanced through simplified and flexible model definition (transistors, cells and blocks).